SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
2.5.10 LCD Bridge Terminal Functions
Table 2-14. LCD Bridge Terminal Functions
SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
This pin is multiplexed between LCD Bridge and SPI.
For LCD Bridge, this pin is either LCD Bridge read/write enable (MPU68 mode) or
LCD_EN_RDB/
SPI_CLK
N3
O/Z
DV DDIO
BH
read strobe (MPU80 mode).
Mux control via the PPMODE bits in the EBSR.
Note: This pin may consume static power if configured as Hi-Z and not pulled high or
low. Prevent current drain by externally terminating the pin.
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS0_E0/
SPI_CS0
P4
I/O/Z
DV DDIO
BH
For LCD Bridge, this pin is either LCD Bridge chip select 0 (MPU68 and MPU80
modes) or enable 0 (HD44780 mode).
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS1_E1/
SPI_CS1
N4
I/O/Z
DV DDIO
BH
For LCD Bridge, this pin is either LCD Bridge chip select 1 (MPU68 and MPU80
modes) or enable 1 (HD44780 mode).
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RW_WRB/
SPI_CS2
P5
I/O/Z
DV DDIO
BH
For LCD, this pin is either LCD Bridge read/write select (HD44780 and MPU68
modes) or write strobe (MPU80 mode).
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RS/
SPI_CS3
N5
I/O/Z
DV DDIO
BH
For LCD, this pin is the LCD Bridge address set-up.
Mux control via the PPMODE bits in the EBSR.
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
P14
N13
P13
N12
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
IPD
DV DDIO
BH
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For LCD Bridge, it is LCD data pin 15.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For LCD Bridge, it is LCD data pin 14.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
For LCD Bridge, it is LCD data pin 13.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
For LCD Bridge, it is LCD data pin 12.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
(1)
(2)
(3)
(4)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-
supply current. Prevent this current by externally terminating it or enabling IPD/IPU, if applicable.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.8.1 , Pullup/Pulldown Resistors .
Specifies the operating I/O supply voltage for each signal
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